Key Highlights

● Quarterly revenue was $1.584 billion against $1.275 billion a year earlier.

● Backlog reached a record $8.1 billion, with $4.2 billion due within 12 months.

● Non-GAAP operating margin rose to 45.5% from 42.8%.

● Full-year 2026 revenue guidance now stands at $6.26 billion to $6.34 billion.

Record backlog and a higher outlook

Cadence Design Systems, Inc. (NASDAQ:CDNS) reported second-quarter 2026 results on 27 July 2026, disclosing a backlog of $8.1 billion at the end of June and raising its full-year revenue guidance. Revenue for the quarter was $1.584 billion, compared with $1.275 billion a year earlier. The combination of strong semiconductor design activity and multi-year customer commitments explains how the backlog reached its current level.

Business and sector

Cadence supplies electronic design automation software, intellectual property and hardware systems used to design chips, circuit boards and complete electronic systems. Its customers include semiconductor makers, hyperscale technology groups and companies in automotive, aerospace and consumer electronics that increasingly design their own silicon.

The sector is a concentrated one, with Cadence and Synopsys (NASDAQ:SNPS) the two largest suppliers. Demand is tied to chip design complexity and to the volume of design projects, both of which have grown as artificial intelligence, data-centre and advanced-node programmes expand. Chief executive Anirudh Devgan described the company as leading the agentic AI transformation in semiconductor design.

Latest reported results

Quarterly revenue rose by about 24% year on year, a figure calculated from the reported amounts. The GAAP operating margin was 28.4%, up from 19.0%, and the non-GAAP operating margin was 45.5%, up from 42.8%. GAAP diluted earnings per share were $1.33, compared with $0.59, and non-GAAP diluted earnings per share were $2.11, compared with $1.65.

Of the $8.1 billion backlog, $4.2 billion is expected to be recognised as revenue within the next 12 months. Operating cash flow for the six months ended 30 June 2026 was $990.7 million, compared with $864.6 million a year earlier. Chief financial officer John Wall cited the record backlog and continued business momentum.

Financial performance and industry context

Cadence raised its 2026 revenue guidance to between $6.26 billion and $6.34 billion, implying growth of 19% at the midpoint. It expects a GAAP operating margin of 27.75% to 28.75%, a non-GAAP operating margin of 43.75% to 44.75%, GAAP earnings per share of $4.76 to $4.86 and non-GAAP earnings per share of $8.05 to $8.15. Operating cash flow is guided at about $2 billion at the midpoint.

For the third quarter, the company guided to a GAAP operating margin of 27.5% to 28.5% and non-GAAP earnings per share of $2.01 to $2.07, without providing a revenue figure in the release.

Backlog matters in this industry because many contracts are multi-year, which gives revenue more visibility than a purely transactional model. It does not remove exposure to timing, as large deals can shift between quarters.

Risks and uncertainties

Cadence depends on the health of the semiconductor industry, and a slowdown in customer investment, whether from cyclical weakness or tighter export controls, could delay design starts. A large share of its revenue comes from a limited number of major customers, and the company competes with Synopsys, Siemens EDA and a growing number of in-house or AI-driven tools. Cadence also sells emulation and prototyping hardware, so results blend recurring licences with upfront hardware sales that can vary between quarters.

Trade restrictions affecting sales to China, integration of acquisitions, and the pace at which new AI-based design tools are adopted all add uncertainty. Backlog is not a guarantee of revenue, because contract terms and customer circumstances can change.

Backlog conversion in focus

The next scheduled event is the third-quarter 2026 report, where results can be tested against the stated margin and earnings guidance. Readers may follow whether backlog continues to grow beyond $8.1 billion, how much of it converts within 12 months, the contribution of hardware and system analysis products, and any change to export-control rules affecting semiconductor design customers.