D-Wave Quantum Inc. filed a Form 8-K with the SEC on August 5, 2026, disclosing a research breakthrough published in the peer-reviewed journal Nature related to its superconducting dual-rail qubit architecture for fault-tolerant quantum computing.

Key Highlights

  • Nature publication: The research, titled "An entangling gate for dual-rail erasure qubits," was published in the peer-reviewed scientific journal Nature.
  • Gate fidelity: The filing reports approximately 99.9% fidelity during two-qubit operations.
  • Gate speed: The two-qubit entangling gate operates with fast gate times of about 500 nanoseconds, according to the filing.
  • Error correction improvement: D-Wave simulations, as disclosed in the filing, indicate the dual-rail architecture could reduce the logical error rate by as much as a factor of 10 for each increment in error correction.
  • Architecture advantage: The filing states the gate preserves the error-correction advantages of D-Wave's superconducting dual-rail qubit architecture through native hardware-level error detection.
  • Common stock listed: D-Wave Quantum Inc. common stock, par value $0.0001 per share, trades under the symbol QBTS on The Nasdaq Stock Market LLC.

D-Wave Quantum Discloses Dual-Rail Qubit Gate Results Under Regulation FD

D-Wave Quantum Inc. (NASDAQ: QBTS) disclosed the announcement under Item 7.01, Regulation FD, of a Form 8-K dated August 5, 2026. The company announced what the filing describes as "a major research breakthrough advancing the path to practical, fault-tolerant gate-model quantum computing," with findings published simultaneously in the journal Nature. The research centers on a new two-qubit entangling gate, which the filing characterizes as "a fundamental building block of quantum computation."

According to the filing, the gate achieves approximately 99.9% fidelity during two-qubit operations and gate times of about 500 nanoseconds. The filing states these results are "enabled by native hardware-level error detection." D-Wave's simulations, as described in the disclosure, indicate its dual-rail architecture could reduce the logical error rate by as much as a factor of 10 for each increment in error correction, which the company states would "significantly reduc[e] the physical qubit overhead required for fault-tolerant quantum computing."

The filing quotes CEO Dr. Alan Baratz as stating the research "demonstrates that D-Wave's dual-rail architecture combines fast superconducting operations with high-fidelity performance while preserving native hardware-level error detection." The filing further notes that D-Wave "believes this work confirms that its path to commercial fault-tolerant quantum computing is practical and achievable." The company attached the full press release as Exhibit 99.1. Per the filing, the information furnished under Item 7.01 is not deemed "filed" for purposes of Section 18 of the Exchange Act and is not subject to the liabilities of that section.

What Was Disclosed

D-Wave Quantum filed an 8-K on August 5, 2026, disclosing a Nature-published research result showing approximately 99.9% fidelity and approximately 500-nanosecond gate times for a two-qubit entangling gate using its superconducting dual-rail qubit architecture, with simulations indicating a potential factor-of-10 logical error rate reduction per error correction increment.